#define  CIM_BASE                0x37000000

#define  TOP_AI_CHOOSE          0x37000000

#define  CIM_ROW_CONFIG_BITS_0                CIM_BASE+0x40
            //B19:0
#define  CIM_ROW_CONFIG_BITS_1                CIM_BASE+0x44
            //B19:0
#define  CIM_ROW_CONFIG_BITS_2                CIM_BASE+0x48
            //B19:0
#define  CIM_ROW_CONFIG_BITS_3                CIM_BASE+0x4C
            //B19:0
#define  CIM_ROW_CONFIG_BITS_4                CIM_BASE+0x50
            //B19:0
#define  CIM_ROW_CONFIG_BITS_5                CIM_BASE+0x54
            //B19:0
#define  CIM_ROW_CONFIG_BITS_6                CIM_BASE+0x58
            //B19:0
#define  CIM_ROW_CONFIG_BITS_7                CIM_BASE+0x5C
            //B19:0
#define  CIM_ROW_CONFIG_BITS_8                CIM_BASE+0x60
            //B19:0
#define  CIM_ROW_CONFIG_BITS_9                CIM_BASE+0x64
            //B19:0
#define  CIM_ROW_CONFIG_BITS_10               CIM_BASE+0x68
            //B19:0
#define  CIM_ROW_CONFIG_BITS_11               CIM_BASE+0x6C
            //B19:0
#define  CIM_ROW_CONFIG_BITS_12               CIM_BASE+0x70
            //B19:0
#define  CIM_ROW_CONFIG_BITS_13               CIM_BASE+0x74
            //B19:0
#define  CIM_ROW_CONFIG_BITS_14               CIM_BASE+0x78
            //B19:0
#define  CIM_ROW_CONFIG_BITS_15               CIM_BASE+0x7C
            //B19:0


#define  CIM_TOP_START                        CIM_BASE+0x80
            //B0
#define  CIM_CFG_CIM_DMA_MODE                 CIM_BASE+0x84
            //B0
#define  CIM_CFG_CIM_WT_MODE                  CIM_BASE+0x88
            //B0
#define  CIM_CFG_CIM_RELU_ENABLE              CIM_BASE+0x8C
            //B0
#define  CIM_SHIFT_NUM                        CIM_BASE+0x90
            //B7:0
#define  CIM_IN_NUM                           CIM_BASE+0x94
            //B7:0
#define  CIM_CFG_TRANSFER_MODE                CIM_BASE+0x98
            //B0       
#define  CIM_CFG_RAM_START_ADDR               CIM_BASE+0x9C
            //B29:0
#define  CIM_CIM_AXI_START_ADDR_32            CIM_BASE+0xa0
            //B31:0
#define  CIM_AXI_START_ADDR_40                CIM_BASE+0xa4
            //B7:0
#define  CIM_TRANSFER_NUM                     CIM_BASE+0xa8
            //B14:0
#define  CIM_CFG_TOP_FINISH                   CIM_BASE+0xaC
            //B0
#define  CIM_CFG_FINISH_CLR                   CIM_BASE+0xb0
            //B0
#define  CIM_CFG_CIM_PE_ENABLE0_31            CIM_BASE+0xb4
            //[7:0][3:0]
#define  CIM_CFG_CIM_PE_ENABLE32_63           CIM_BASE+0xb8
            //[15:8][3:0]
